International Journal of Emerging Research in Science, Engineering, and Management
Vol. 1, Issue 4, pp. 27-32, October 2025.
This work is licensed under a Creative Commons Attribution 4.0 International License.
Design and Simulation of Low-Power VLSI Multiplier Using Modified Booth Algorithm
Zonnawada Chaithanya
Usthulamuri Penchalaiah
Assistant Professor, Department of ECE, Geethanjali Institute of Science and Technology, Nellore, India
Professor, Dean of SA&H & HOD, Department of ECE, Geethanjali Institute of Science and Technology, Nellore, India
Abstract: Efficient multiplication is crucial in digital signal processing and arithmetic computing systems, particularly on low-power, portable embedded platforms. The Modified Booth algorithm effectively reduces the number of partial products and improves performance in multiplication operations. This work presents the design and simulation of a low-power VLSI multiplier using a modified Booth encoding scheme, optimized for reduced switching activity and minimized hardware complexity. The proposed architecture is implemented in Verilog HDL and evaluated for power, delay, and area using industry-standard EDA tools. Simulation results demonstrate significant power savings and reduced critical path delay compared to conventional multipliers, making the design well-suited for high-performance and energy-efficient digital systems.
Keywords: Artificial Intelligence, Employee Productivity, Small and Medium-sized Enterprises, Organizational Performance, Workplace Innovation.
References:
- V. Gundavarapu, P. Gowtham, A. A. Angeline, and P. Sasipriya, “Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications,” Microprocessors and Microsystems, vol. 106, p. 105036, Feb. 2024, doi: 10.1016/j.micpro.2024.105036.
- P. J. Edavoor, A. K. Samantaray, and A. D. Rahulkar, “Design of floating point multiplier using approximate hybrid Radix-4/ Radix-8 booth encoder for image analysis,” e-Prime – Advances in Electrical Engineering Electronics and Energy, vol. 8, p. 100546, Apr. 2024, doi: 10.1016/j.prime.2024.100546.
- P. Thilagavathi, S. Senthil Kumar, D. Gowthami, and A. Sridevi, “All Pass Transformation based Variable Digital Filter design using Low Power Approximate Floating Point Adder and Low Power Compressor based Approximate Multiplier,” Integration, p. 102344, Jan. 2025, doi: 10.1016/j.vlsi.2025.102344.
- N. Anuradha, S. K. Patel, and S. K. Singhal, “An area-delay efficient single-precision floating-point multiplier for VLSI systems,” Microprocessors and Microsystems, vol. 98, p. 104798, Feb. 2023, doi: 10.1016/j.micpro.2023.104798.
- D. K. J. Rajanediran, G. B. C, P. K, and M. Ramkumar, “Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application,” Integration, vol. 98, p. 102215, May 2024, doi: 10.1016/j.vlsi.2024.102215.
- A. Mandloi and S. Pawar, “Power and delay efficient FIR filter design using ESSA and VL-CSKA based booth multiplier,” Microprocessors and Microsystems, vol. 86, p. 104333, Aug. 2021, doi: 10.1016/j.micpro.2021.104333.
- B. Boro, K. M. Reddy, Y. B. N. Kumar, and M. H. Vasantha, “Approximate radix-8 Booth multiplier for low power and high speed applications,” Microelectronics Journal, vol. 101, p. 104816, May 2020, doi: 10.1016/j.mejo.2020.104816.
- S. -S. Ahmadpour et al., “Design and implementation of a nano-scale high-speed multiplier for signal processing applications,” Nano Communication Networks, vol. 41, p. 100523, Jun. 2024, doi: 10.1016/j.nancom.2024.100523.
- G. Haridas and D. S. George, “Area efficient low power modified booth multiplier for FIR filter,” Procedia Technology, vol. 24, pp. 1163-1169, Jan. 2016, doi: 10.1016/j.protcy.2016.05.070.
- V. S. Chowdam, S. B. Potladurty, and P. R. Karipireddy, “Design and evaluation of Clock-Gating-Based Approximate Multiplier for Error-Tolerant Applications,” Memories – Materials Devices Circuits and Systems, p. 100123, Jan. 2025, doi: 10.1016/j.memori.2025.100123.