An Efficient Multiplier Design Employing Hybrid Adder Logic

International Journal of Emerging Research in Science, Engineering, and Management
Vol. 2, Issue 3, pp. 142-148, March 2026.

https://doi.org/10.58482/ijersem.v2i3.18

This work is licensed under a Creative Commons Attribution 4.0 International License.

An Efficient Multiplier Design Employing Hybrid Adder Logic

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S Sreelatha

K Lalitha

S Kavya

S Naresh Kumar

C Mohana

Department of ECE, Siddartha Institute of Science and Technology, Puttur, AP, India.

Abstract: Modern electronic systems demand compact, high-speed, and low-power designs to meet the increasing computational requirements of digital applications. Arithmetic operations, especially multiplication, significantly influence the overall performance of such systems. In VLSI-based signal processing, achieving fast and power-efficient multiplication is essential for real-time processing and optimized hardware performance. This paper presents a novel high-speed multiplier design that employs a hybrid adder architecture, integrating the advantages of the Han–Carlson Adder (HCA) and the Knowles Adder (KA). The proposed hybrid structure effectively reduces propagation delay and improves performance by balancing the trade-offs between speed, power, and area. Simulation results confirm that the proposed design achieves superior performance compared to conventional multiplier architectures. Hence, this hybrid multiplier is highly suitable for high-performance VLSI and signal processing applications where speed and efficiency are critical.

Keywords: Hybrid Multiplier, Hybrid Adder, Han-Carlson Adder, Knowles Adder, High-Speed Arithmetic.

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This article is part of Volume 2, Issue 3 (March 2026)