Design and Implementation of a Low-Power ALU Using Quaternary Reversible Logic for Optimized Quantum Cost

International Journal of Emerging Research in Science, Engineering, and Management

Vol. 2, Issue 3, pp. 291–296, March 2026

https://doi.org/10.58482/ijersem.v2i3.37

This work is licensed under a Creative Commons Attribution 4.0 International License .

Design and Implementation of a Low-Power ALU Using Quaternary Reversible Logic for Optimized Quantum Cost

R Leelavathi, K Lakshmi Vyshnavi, P Nagendra, P Prabhanjan Kumar, Mahamkali Mounika, Thota Kavya

Department of ECE, Siddartha Institute of Science and Technology, Puttur, India.

Abstract

Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss. Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic. This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers. The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach. The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures. Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications. The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.

Keywords: Low-power ALU, Reversible Logic, Quantum Cost, Verilog HDL, Xilinx Vivado.

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DOI: https://doi.org/10.58482/ijersem.v2i3.37

Open Access • Peer Reviewed Article

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This article is part of Volume 2, Issue 3 (March 2026)

2026-03-31