Verilog-Based Automatic Bus Ticketing System using a Pipelining Approach with Clock Gating Mechanism

Abstract: This paper presents the design and implementation of a fully automated digital Bus Ticketing System (BTS) using a hierarchical Verilog HDL architecture. The proposed system addresses the need for efficient, reliable, and user-friendly fare collection in modern public transportation by integrating real-time ticket selection, monetary transaction processing, and dynamic display management. The architecture comprises five primary modules: Ticket Selection for route, price, and quantity configuration; Rupees Calculation for cumulative currency tracking; Return Processing for change computation and ticket validation; Display Interface featuring multiplexed 7-segment displays; and Clock Gating circuitry for power optimization. The system supports dual-route configurations with three pricing tiers (₹3, ₹5, ₹10) and variable ticket quantities, accepting ₹5 and ₹10 denomination inputs. A finite state machine-based Return Processing module validates transactions against six distinct ticket combinations, indicated through dedicated LED outputs, while automatically computing change for overpayment scenarios. The complete system incorporates a flip-flop-based clock gating mechanism to reduce dynamic power consumption during idle states. Implementation is carried out using Verilog HDL with behavioral and structural modeling techniques, synthesized and verified on [Xilinx Artix-7/Spartan-7 FPGA platform]. Simulation results demonstrate successful transaction processing with accurate fare calculation, change dispensing, and real-time visual feedback through multiplexed display architecture cycling through six information states at programmable refresh rates.